1. Technical Field
The present invention relates generally to a phase-locked loop (PLL) and, more particularly, to a phase detector for self-controlling offset current: and to a PLL including the same.
2. Description of Related Art
Semiconductor devices that operate in synchronization with an external clock, such as semiconductor memories or central processing units (CPUs), generate an internal clock using a clock buffer-and a clock driver. The internal clock is delayed a predetermined period of time in comparison to the external clock, thus degrading high frequency operating characteristics of such semiconductor devices.
That is, an access time period required to output data after an external clock has been input is always longer than a time period required to generate an internal clock after the external clock has been generated, thus adversely affecting the speed of a semiconductor memory device. To avoid such low performance of a semiconductor memory device, a PLL is required to accurately synchronize an internal clock with an external clock.
Typically, a PLL is a nonlinear analog device that uses a negative feedback loop to make the phase difference between an input signal and an output signal smaller or, preferably, approximately equal to zero. The phase difference between both signals becomes smaller and smaller, which also makes the frequency of both signals equal. PLLs are widely used as an indispensable interface for clock synchronization in high-speed communication systems or semiconductor memory systems. FIG. 1 is a block diagram of a conventional PLL. The PLL includes a phase detector (PD) 3, a loop filter 5, and a voltage controlled oscillator (VCO) 7.
The PD 3 senses a phase difference between an external clock MODOUT and an internal clock MIXOUT output from the VCO 7 and outputs a current signal PDOUT corresponding to the phase difference to the loop filter 5. The loop filter 5, in turn, outputs a DC component that excludes an AC component in response to the output signal PDOUT of the PD 3. The VCO 7 outputs the internal clock MIXOUT in response to the output signal of the loop filter S.
FIG. 2 is the circuit diagram of the PD 3 shown in FIG. 1. The PD 3 includes a Gilbert multiplier cell or Gilbert core block 11. The mixer-type PD 3 using the Gilbert core block 11 has a drawback in that it cannot reduce the difference in frequency between an external clock MODout and an internal clock MIXout when the phase is out of lock.
Conventionally, to overcome such a drawback, an offset current source 10 continuously outputs a constant offset current to node n3 that is proportional to a reference; current signal Iref from an initial operation of the PLL, thus sweeping down the frequency of the internal clock to be in lock with the external clock and controlling the locking time.
However, since the conventional phase detector 3 of FIG. 2 (and a PLL including the same) outputs a constant offset current to the node n3 when the PLL is in lock, unnecessary current is consumed and repeated determination must be made to identify an optimum offset current.
To solve the above and other related problems of the prior art, there is provided a phase detector and a phase-locked loop (PLL) including the same. The phase detector (and PLL) locks phase quickly and steadily while reducing unnecessary offset current.
According to an aspect of the invention, there is provided a phase detector that includes a Gilbert Cell, a converter, a variable current source, and a variable current source controller. The Gilbert cell includes a Gilbert core block for outputting a signal proportional to a phase difference between first and second input signals to a first output terminal, and a current source for determining a current flowing in the first output terminal. The current source is controlled by a reference current signal. The converter outputs a current to a second output terminal in response to the signal output from the first output terminal. The variable current source varies the current output to the second output terminal. The variable current source controller controls the variable current source in response to the first and second input signals.
Preferably, the variable current source controller includes a counter for outputting a number of first edges of the first input signal that exist between first edges of first and second clock pulses of the second input signal. Moreover, it is preferable if the variable current source outputs a current proportional to an output signal of the variable current source controller and the reference current signal.
These and other aspects, features and advantages of the present invention will become apparent from the following detailed description of preferred embodiments, which is to be read in connection with the accompanying drawings.